Energy-Delay Tradeoff in Low Power, High Speed Digital Processors
نویسندگان
چکیده
Previous research has introduced novel energy saving techniques such as the use of multiple VDD and VTH transistors, as well as transistor sizing, to limit storage energy and standby power. These techniques have been used to lower the power consumed in the non-critical paths of a design for a given performance specified by the critical path. In this report, a proposal to investigate how dual-supply and dual-voltage techniques affect power consumption and delay in critical paths of datapath designs is presented.
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