Energy-Delay Tradeoff in Low Power, High Speed Digital Processors

نویسندگان

  • Danijela Cabric
  • Nathan Chan
  • Richard Lu
چکیده

Previous research has introduced novel energy saving techniques such as the use of multiple VDD and VTH transistors, as well as transistor sizing, to limit storage energy and standby power. These techniques have been used to lower the power consumed in the non-critical paths of a design for a given performance specified by the critical path. In this report, a proposal to investigate how dual-supply and dual-voltage techniques affect power consumption and delay in critical paths of datapath designs is presented.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Ultra-Low-Energy DSP Processor Design for Many-Core Parallel Applications

Background and Objectives: Digital signal processors are widely used in energy constrained applications in which battery lifetime is a critical concern. Accordingly, designing ultra-low-energy processors is a major concern. In this work and in the first step, we propose a sub-threshold DSP processor. Methods: As our baseline architecture, we use a modified version of an existing ultra-low-power...

متن کامل

ضرب‌کننده و ضرب‌جمع‌کننده پیمانه 2n+1 برای پردازنده سیگنال دیجیتال

Nowadays, digital signal processors (DSPs) are appropriate choices for real-time image and video processing in embedded multimedia applications not only due to their superior signal processing performance, but also of the high levels of integration and very low-power consumption. Filtering which consists of multiple addition and multiplication operations, is one of the most fundamental operatio...

متن کامل

Switched-Capacitor Dynamic Threshold PMOS (SC-DTPMOS) Transistor for High Speed Sub-threshold Applications

This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...

متن کامل

Design and Analysis of an Ultra Low Power Clocked Regenerative Comparator

This paper explores various available comparator designs and proposes an improved ultra low power comparator with reduced delay at 90nm. Dynamic comparators which are extensively used in data converters and digital signal processors require low power consumption and high speed. A clock based dynamic comparator is simulated with delay of 64ps and power dissipation of 31.8μW. The comparator struc...

متن کامل

High-Speed Ternary Half adder based on GNRFET

Superior electronic properties of graphene make it a substitute candidate for beyond-CMOSnanoelectronics in electronic devices such as the field-effect transistors (FETs), tunnel barriers, andquantum dots. The armchair-edge graphene nanoribbons (AGNRs), which have semiconductor behavior,are used to design the digital circuits. This paper presents a new design of ternary half a...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2002